The present invention relates to an image size reducing method of reducing an entered image in the vertical direction, and displaying it in an image display device, and an apparatus using the same method.
As an example of reducing an image size in the vertical direction and displaying said reduced image size in an image display device, a conventional image size reducing method is described below by referring to FIG. 14, FIG. 15, FIG. 16, and FIG. 18.
To begin with, a first prior art of image size reducing method is described.
An image display device 2 in FIG. 14 receives a vertical synchronizing signal 21, a horizontal synchronizing signal 26, an enable signal 27, and a clock signal 28, and displays image data 20 sequentially from the upper left corner to the lower right corner of an image display area. A basic decimating operation is used to recognize the beginning of a horizontal scanning line on the basis of the horizontal synchronizing signal 26, and to display the image data 20 in the image display area when the enable signal 27 provided by gate circuit 1 is active. That is, as shown in FIG. 15, a horizontal synchronizing signal 22 and one or more signals of the entered enable signal 23 and clock signal 24 are gated by the gate circuit 1, and an enable signal 27, a clock signal 28, and a horizontal synchronizing signal 26 are issued, and, as a result, each signal corresponding to image data K of K-th line is decimated by a gate signal 25.
A specific example of the gate circuit 1 is a gate circuit 3 in FIG. 16. By such decimating, image data (K+1) is displayed in the image display device 2 in the next horizontal scanning line of displaying image data (Kxe2x88x921) without displaying image data K.
By thus decimating the horizontal synchronizing signal 22 and enable signal 23 at the timing corresponding to an arbitrary horizontal scanning line, the image data 20 corresponding to the decimated horizontal synchronizing signal 26 and decimated enable signal 27 is displayed in the image display device 2 in a decimated state. By varying the decimating rate of the horizontal synchronizing signal 22 and enable signal 23, the number of lines in the vertical direction of the image data displayed in the image display device 2 can be freely decreased.
Thus, as far as at least the horizontal synchronizing signal 22 and one or both of the enable signal 23 and clock signal 24 are decimated, even if the image data 20 is not decimated, the image data in that portion is not displayed in the display device, and therefore, for example, certain LCD, PDP and corresponding display device can be used as the image display device to be used herein.
By making use of this method, hitherto, horizontal synchronizing signal 22 and one signal or both of the enable signal 23 and clock signal 24 are decimated in fixed horizontal scanning lines in each frame, and the entered image was reduced and displayed in the image display device 2.
In a second prior art, horizontal scanning lines to be decimated are selected arbitrarily in the horizontal scanning lines for composing the image and only the image data other than said selected horizontal scanning lines is written into the memory. The image reduced by a number of the decimated horizontal scanning lines is stored in the memory and the reduced image size can be displayed in the image display device by sequentially reading out the image data.
After writing image data of all horizontal scanning lines for composing the image into the memory, a reduced image size can be displayed in the image display device by reading out sequentially only the image data other than the horizontal scanning lines arbitrarily selected for decimating, similarly.
In the conventional method, however, the line numbers of the selected horizontal lines on the basis of the vertical synchronizing signals are fixed in all frames. That is, image size reduction was realized by decimating horizontal scanning lines always at the same positions in every frame.
In a third prior art, there is a method using a digital filter, and said image size reducing method in the vertical direction by using two-tap digital filter showing in FIG. 17 is described below. Herein, a delay circuit 4 in FIG. 17 is a delay element for delaying the entered image data by time of one horizontal scanning line.
In FIG. 18, line s, line (s+1), line (s+2), and line (s+3) are horizontal scanning lines for composing an original image before reduction, and pixels 29a, 29b, 29c, 29d are pixels belonging to individual horizontal scanning lines. The image data expressing the pixel value of each pixel is expressed by a, b, c and d individually.
The digital filter in FIG. 17 calculates pixel data a and pixel data b using formula 1, and produces pixel data e of pixel 29e of a newly created line r.
e=axc3x97p1+bxc3x97q1 (where p1 and q1 are integers)xe2x80x83xe2x80x83[1]
By operating this calculation on image data of all pixels of line s and line (s+1), image data of all pixels for composing line r is created newly. Herein, by replacing lines s and (s+1) by line r, the number of lines can be decreased. Similarly, from the horizontal scanning lines of line (s+2) and line (s+3), image data f of pixel 29f of horizontal scanning lines of line (r+1) can be newly created using formula 2.
f=cxc3x97p2+dxc3x97q2 (where p2 and q2 are integers)xe2x80x83xe2x80x83[2]
Herein, the number of lines can be decreased by the same process as process in the above operation.
Similarly, by operation of formula 1, formula 2 sequentially, the vertical size of the image can be reduced.
Herein, p1, p2, . . . , q1, q2, . . . are integers determined by the reduction rate.
By determining the number of operations by the reduction rate in the vertical direction, the original image can be reduced to a desired size.
The conventional image size reducing methods are described so far, but when the original image size is reduced in the vertical direction by employing the first method and second method, since the horizontal scanning lines to be decimated are always fixed in each frame, the image data of the decimated horizontal scanning lines is completely unseen in the image display device. For example, if the horizontal synchronizing signal corresponding to the image of the horizontal line of which width is equivalent to the width of one horizontal scanning line is decimated, the horizontal line is completely eliminated. Moreover, a fine character may be considerably deformed and is very hard to be seen.
In the third method, the multiplier and line memory are needed, and the circuit is large and complicated. And, if the number of taps of digital filter is small, deterioration of frequency characteristic is significant, the edge in the vertical direction is vague, and it causes a problem of deterioration of image quality when a still image such as a personal computer image is reduced.
The invention is intended to solve such problems, and it is hence an object thereof to present an apparatus for realizing reduction of image size in the vertical direction and the image size reducing method, suppressing loss of horizontal line, deformation of fine character, distortion of image in the vertical direction, and vague edge in the vertical direction, in a simple circuit.
The image size reducing method of the invention comprises a counter for counting horizontal synchronizing signals of entered image signals, a gate signal generating circuit for generating a gate signal using the count value of the counter, the reduction rate in the vertical direction of the image, the vertical synchronizing signal and horizontal synchronizing signal, and a gate circuit for decimating horizontal synchronizing signal H at least one of enable signal E and clock signal C by using the gate signal, and an entered signal is displayed in an image display device by using the vertical synchronizing signal and decimated horizontal synchronizing signal Hxe2x80x2 and one of a combination of decimated enable signal Exe2x80x2 and clock signal C, a combination of the enable signal E and decimated clock signal Cxe2x80x2, or a combination of decimated enable signal Exe2x80x2 and decimated clock signal Cxe2x80x2.
There are two kind of means in the image size reducing apparatus of the invention roughly. First means comprises a counter for counting vertical synchronizing signals, a gate signal generating circuit for generating a gate signal using the count value of the counter, the reduction rate in the vertical direction of the image size, the vertical synchronizing signal and horizontal synchronizing signal, a gate circuit for decimating horizontal synchronizing signal H and at least one of enable signal E and clock signal C, by using the gate signal, and an image display device driven by the vertical synchronizing signal and decimated horizontal synchronizing signal Hxe2x80x2 and one of a combination of decimated enable signal Exe2x80x2 and clock signal C, a combination of the enable signal E and decimated clock signal Cxe2x80x2, or a combination of decimated enable signal Exe2x80x2 and decimated clock signal Cxe2x80x2.
The image size reducing apparatus using this structure described above is further classified into two apparatuses. One is to reduce the image size by decimating the signals relating to predetermined line numbers.
The other one has a structure added a delay circuit for delaying the image data, a subtraction circuit for calculating the difference value of the two pixel values, and an adder for adding the difference value to the above constitution and reduces the image size is reduced by decimating the signals relating to the selected horizontal scanning lines, using the line difference value determined from the difference value of the pixels of two adjacent horizontal scanning lines.
The former is described in embodiment 1, and the latter, in embodiment 3.
Second means of the image size reducing apparatus of the invention comprises a counter for counting vertical synchronizing signals of image signals, a memory for storing image data of image signals, a memory control unit for controlling to store the image data selectively into the memory or to read out the image data selectively from the memory, and an image display unit for displaying the read image data.
The image size reducing apparatus using this structure is further classified into two types. One is to reduce the image size by controlling to write image data of the predetermined line number into the memory or to read out the image data from the memory.
The other one has a structure added a delay circuit for delaying the image data, a subtraction circuit for calculating the difference value of the image data between the line before delay and image data after delay, and an adder for adding the difference value to the above structure and reduces the image size by controlling to store the image data selected using the line difference value obtained from the difference value between the pixel data of two adjacent horizontal scanning lines into the memory or to read out the image data from the memory.
The former is described in embodiment 2, and the latter, in embodiment 4.